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A global code scheduling technique using guarded PDG
http://hdl.handle.net/2065/818
http://hdl.handle.net/2065/81864ecaaf1-4077-4323-9df0-a74bd7ebb5ae
名前 / ファイル | ライセンス | アクション |
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00472253.pdf (596.6 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2008-04-23 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | A global code scheduling technique using guarded PDG | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Koseki, Akira
× Koseki, Akira× Komatsu, Hideaki× Fukazawa, Yoshiaki |
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書誌情報 |
Algorithms and Architectures for Parallel Processing, 1995. ICAPP 95. IEEE First ICA/sup 3/PP. IEEE First International Conference on 巻 Volume 2, p. 661-669, 発行日 1995-04 |
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権利 | ||||||
権利情報 | Copyright: Institute of Electrical and Electronic Engineers (IEEE) | |||||
日本十進分類法 | ||||||
主題 | 007.6406 | |||||
米国議会図書館件名標目 | ||||||
主題 | Parallel processing (Electronic computers)--Congresses | |||||
米国議会図書館件名標目 | ||||||
主題 | Computer algorithms--Congresses | |||||
米国議会図書館件名標目 | ||||||
主題 | Computer architecture--Congresses | |||||
出版者 | ||||||
出版者 | Institute of Electrical and Electronic Engineers | |||||
資源タイプ | ||||||
内容記述 | text | |||||
関連情報 | ||||||
関連名称 | IEEE CNF |