{"created":"2023-07-27T08:05:01.713256+00:00","id":27598,"links":{},"metadata":{"_buckets":{"deposit":"6a5ba6d2-209f-449c-98ab-976145e5d433"},"_deposit":{"created_by":3,"id":"27598","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"27598"},"status":"published"},"_oai":{"id":"oai:waseda.repo.nii.ac.jp:00027598","sets":["5073:143:1975:1976"]},"author_link":["48012","47962","47960","48013","48014"],"item_10003_biblio_info_90":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2002-12","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"176","bibliographicPageStart":"171","bibliographicVolumeNumber":"1","bibliographic_titles":[{"bibliographic_title":"Circuits and Systems, 2002. APCCAS '02. 2002 Asia-Pacific Conference on"}]}]},"item_10003_description_123":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"subitem_description":"text","subitem_description_type":"Other"}]},"item_10003_publisher_116":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_10003_relation_95":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isIdenticalTo","subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/APCCAS.2002.1114930","subitem_relation_type_select":"DOI"}}]},"item_10003_rights_96":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright: Institute of Electrical and Electronic Engineers (IEEE)"}]},"item_10003_text_144":{"attribute_name":"URI","attribute_value_mlt":[{"subitem_text_value":"http://hdl.handle.net/2065/10689"}]},"item_10003_version_type_99":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Miyaoka, Yuichiro"}],"nameIdentifiers":[{"nameIdentifier":"48012","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Choi, Jinku"}],"nameIdentifiers":[{"nameIdentifier":"48013","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Togawa, Nozomu"}],"nameIdentifiers":[{"nameIdentifier":"47960","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"1000030298161","nameIdentifierScheme":"NRID","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000030298161"}]},{"creatorNames":[{"creatorName":"Yanagisawa, Masao"}],"nameIdentifiers":[{"nameIdentifier":"47962","nameIdentifierScheme":"WEKO"},{"nameIdentifier":"1000030170781","nameIdentifierScheme":"NRID","nameIdentifierURI":"https://nrid.nii.ac.jp/ja/nrid/1000030170781"}]},{"creatorNames":[{"creatorName":"Otsuki, Tatsuo"}],"nameIdentifiers":[{"nameIdentifier":"48014","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2016-11-28"}],"displaytype":"detail","filename":"P4-02-004.pdf","filesize":[{"value":"608.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"P4-02-004.pdf","url":"https://waseda.repo.nii.ac.jp/record/27598/files/P4-02-004.pdf"},"version_id":"00d9b382-b383-4a00-9a4d-595acbb11c0e"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"conference paper","resourceuri":"http://purl.org/coar/resource_type/c_5794"}]},"item_title":"An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions","subitem_title_language":"en"}]},"item_type_id":"10003","owner":"3","path":["1976"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-04-28"},"publish_date":"2008-04-28","publish_status":"0","recid":"27598","relation_version_is_last":true,"title":["An algorithm of hardware unit generation for processor core synthesis with packed SIMD type instructions"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2024-01-15T05:19:09.222081+00:00"}